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Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Contextwccftech.comView all sources →
Limited signal. This briefing is built from 2 sources — treat the summary as preliminary, not a comprehensive newsroom report.

Also known as risc-v international·risc-v cpu·risc-v processor·risc-v architecture·risc-v chip

1.5 Activity score up · 2d
1.9 Peak score 3d window
2 Sources · 2 signals
Latest source signal
3d First on radar
Key Takeaway Alibaba’s XuanTie C950 RISC-V chip is being framed as a native AI workload platform, now reportedly running Qwen-3.8 27B at up to 30 tps, alongside rapid growth in RISC-V MCU options.
AI summary · grounded in cited sources
SourcesWCCFTechCNX SoftwareView all sources →
AI model on RISC-V Alibaba XuanTie C950 RISC-V MCU expansion Tiny dev boards risc-v international
Positive 78/100
Themes
AI model on RISC-VAlibaba XuanTie C950RISC-V MCU expansionTiny dev boards
AI Brief

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

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Top 1 signals · recent activity
WCCFTech · 9h ago
Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Recent signals

  • Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds wccftech.com
  • Alibaba's RISC-V CPU, XuanTie C950, Runs Qwen-3.8 27B at 30 tps WCCFTech
  • WCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM CNX Software
  • Comu is a $6 tiny CH32V203 RISC-V development board that fits inside a USB port CNX Software
Source-backed brief 1 article across 1 publication · brief is source backed Show all sources
WCCFTech · 1 article

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wccftech.com

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Alibaba's XuanTie C950 chip hits 30 tokens/second, with a 1.9-second first-token latency, on Qwen-3.8 27B - no emulation layer required.

17h ago Rohail Saleem
cnx-software.com

WCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM - CNX Software

WCH CH32V407 and CH32V467 are new 200 MHz RISC-V microcontrollers with a built-in 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbps) host

6d ago Jean-Luc Aufranc (CNXSoft)

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WCCFTech 1 article

Tracking: Alibaba’s TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Alibaba’s TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds
Discovery

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From the channels we track
RISC-V Summit 2019: 23 Avoiding Amdahl's Law RISC-V Architecture Exploration for AI & ML Compute RISC-V International The Year of RISC-V in a laptop TechTechPotato Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann RISC-V International Andes Technology Interview at RISC-V Summit Europe 2023 RISC-V International

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Hacker News · u/mrLSD-dev · 

F# RISC-V v0.6.0 released

F# RISC-V v0.6.0 released

4

People also ask

Common questions on RISC-V, surfaced from across the indexed web.

How is video output generated and synchronized at 320x200 resolution from individual single-pixel MCUs?

Each MCU in bitluni’s build is assigned to generate one pixel of the 320x200 (QVGA) frame, so the full image is produced in parallel by 8,192 CH570 RISC-V microcontrollers. The cluster’s per-pixel outputs are combined to form the frame at QVGA resolution and driven as the video signal; timing and synchronization are achieved by coordinating the MCUs so they output their pixel values in the correct order for the 320x200 scanout. Answered

Engineer builds his own graphics card because modern GPUs are too expensive
What’s Up with RISE?

So what’s this impressive list of RISC-V movers and shakers actually doing with RISE?  The RISE Project focuses on commercial product readiness, key for the adoption of RISC-V technologies in market segments such as mobile, datacenter, consumer electronics, datacenter and automotive. RISE's mission is to accelerate the development of open source software for the RISC-V architecture. Members share a roadmap, technical contributions, staffing and funding for critical projects across a wide set of project categories, such as compilers and toolchains, debug and profiling, Linux distribution integr

Rising to the challenge of RISC-V software readiness
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