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RISC-V

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People are highlighting fresh RISC-V hardware progress: Alibaba’s XuanTie C950 running Qwen-3.8 27B at 30 tps, alongside new RISC-V MCU offerings from WCH with integrated Ethernet/USB PHY features. Hobbyist attention is also focused on very small, USB-port-sized RISC-V dev boards like Comu.

ContextWCCFTechCNX SoftwareView all sources →
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Also known as risc-v international·risc-v cpu·risc-v processor·risc-v architecture·risc-v chip

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Key Takeaway RISC-V momentum is spanning from edge AI performance on Alibaba’s XuanTie C950 to highly integrated WCH MCUs and ultra-compact USB dev boards.
AI summary · grounded in cited sources
AI on RISC-V MCU integration Tiny dev boards risc-v international risc-v cpu
Positive 78/100
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AI on RISC-VMCU integrationTiny dev boards
AI Brief

Alibaba's RISC-V CPU, XuanTie C950, Runs Qwen-3.8 27B at 30 tps

People are highlighting fresh RISC-V hardware progress: Alibaba’s XuanTie C950 running Qwen-3.8 27B at 30 tps, alongside new RISC-V MCU offerings from WCH with integrated Ethernet/USB PHY features. Hobbyist attention is also focused on very small, USB-port-sized RISC-V dev boards like Comu.

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r/LocalLLaMA · 18h ago
Alibaba's RISC-V CPU, XuanTie C950, Runs Qwen-3.8 27B at 30 tps

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wccftech.com

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Alibaba's XuanTie C950 chip hits 30 tokens/second, with a 1.9-second first-token latency, on Qwen-3.8 27B - no emulation layer required.

22h ago Rohail Saleem
cnx-software.com

Comu is a $6 tiny CH32V203 RISC-V development board that fits inside a USB port - CNX Software

Over the years, we have seen several tiny “omu” USB boards that share this “fits-in-a-USB-port” form factor. It started with the Tomu, based on a Silicon

9d ago Debashis Das
cnx-software.com

WCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM - CNX Software

WCH CH32V407 and CH32V467 are new 200 MHz RISC-V microcontrollers with a built-in 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbps) host

6d ago Jean-Luc Aufranc (CNXSoft)

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From the channels we track
RISC-V Summit 2019: 23 Avoiding Amdahl's Law RISC-V Architecture Exploration for AI & ML Compute RISC-V International The Year of RISC-V in a laptop TechTechPotato Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann RISC-V International Andes Technology Interview at RISC-V Summit Europe 2023 RISC-V International

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Recent threads on Reddit and Hacker News that mention RISC-V.

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Hacker News · u/mrLSD-dev · 

F# RISC-V v0.6.0 released

F# RISC-V v0.6.0 released

4

People also ask

Common questions on RISC-V, surfaced from across the indexed web.

How is video output generated and synchronized at 320x200 resolution from individual single-pixel MCUs?

Each MCU in bitluni’s build is assigned to generate one pixel of the 320x200 (QVGA) frame, so the full image is produced in parallel by 8,192 CH570 RISC-V microcontrollers. The cluster’s per-pixel outputs are combined to form the frame at QVGA resolution and driven as the video signal; timing and synchronization are achieved by coordinating the MCUs so they output their pixel values in the correct order for the 320x200 scanout. Answered

Engineer builds his own graphics card because modern GPUs are too expensive
What’s Up with RISE?

So what’s this impressive list of RISC-V movers and shakers actually doing with RISE?  The RISE Project focuses on commercial product readiness, key for the adoption of RISC-V technologies in market segments such as mobile, datacenter, consumer electronics, datacenter and automotive. RISE's mission is to accelerate the development of open source software for the RISC-V architecture. Members share a roadmap, technical contributions, staffing and funding for critical projects across a wide set of project categories, such as compilers and toolchains, debug and profiling, Linux distribution integr

Rising to the challenge of RISC-V software readiness
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