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RISC-V

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Recent headlines focus on RISC-V momentum across both software and hardware: Linux 7.2 highlights RISC-V alongside Arm and MIPS, while multiple companies are pushing new 64-bit and MCU RISC-V designs with performance and connectivity features (e.g., StarFive’s Dubhe-100 and WCH’s Fast Ethernet MCU).

ContextCNX SoftwareCNX SoftwareView all sources →
Limited signal. This briefing is built from 1 source — treat the summary as preliminary, not a comprehensive newsroom report.

Also known as risc-v international·risc-v cpu·risc-v processor·risc-v architecture·risc-v chip

0.6 Activity score down · 3d
1.9 Peak score 3d window
1 Sources · 1 signals
Latest source signal
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Key Takeaway RISC-V is being advanced simultaneously in operating-system support and in new high-integration, performance-focused hardware cores/MCUs.
AI summary · grounded in cited sources
Linux support 64-bit RISC-V cores RISC-V MCU connectivity risc-v international risc-v cpu
Positive 78/100
Themes
Linux support64-bit RISC-V coresRISC-V MCU connectivity
AI Brief

Linux 7.2 release – Main changes, Arm, RISC-V, and MIPS architectures

Recent headlines focus on RISC-V momentum across both software and hardware: Linux 7.2 highlights RISC-V alongside Arm and MIPS, while multiple companies are pushing new 64-bit and MCU RISC-V designs with performance and connectivity features (e.g., StarFive’s Dubhe-100 and WCH’s Fast Ethernet MCU).

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Top 1 signals · recent activity
CNX Software · 21h ago
Linux 7.2 release – Main changes, Arm, RISC-V, and MIPS architectures

Recent signals

  • Linux 7.2 release – Main changes, Arm, RISC-V, and MIPS architectures CNX Software
  • StarFive Dubhe-100 – A 64-bit, RVA23-compliant RISC-V core for high-performance applications CNX Software
  • WCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM CNX Software
Source-backed brief 1 article across 1 publication · brief is source backed Show all sources
CNX Software · 1 article

Latest from across the web

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cnx-software.com

StarFive Dubhe-100 - A 64-bit, RVA23-compliant RISC-V core for high-performance applications - CNX Software

StarFive has launched a new high-performance 64-bit RISC-V core from the Dubhe family with the RVA23-compliant Dubhe-100 designed for servers and HPC, as

2d ago Jean-Luc Aufranc (CNXSoft)
cnx-software.com

Linux 7.2 release - Main changes, Arm, RISC-V, and MIPS architectures - CNX Software

Linus Torvalds released Linux 7.2 on LKML last Sunday: Well, this last week of the release was - once again - bigger than I would have wished for, but

21h ago Jean-Luc Aufranc (CNXSoft)
cnx-software.com

WCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM - CNX Software

WCH CH32V407 and CH32V467 are new 200 MHz RISC-V microcontrollers with a built-in 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbps) host

9d ago Jean-Luc Aufranc (CNXSoft)
wccftech.com

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Alibaba's XuanTie C950 chip hits 30 tokens/second, with a 1.9-second first-token latency, on Qwen-3.8 27B - no emulation layer required.

3d ago Rohail Saleem

What each outlet is saying

Source-by-source view of what publications and communities are surfacing right now.

Discovery

Videos

From the channels we track
RISC-V Summit 2019: 23 Avoiding Amdahl's Law RISC-V Architecture Exploration for AI & ML Compute RISC-V International Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann RISC-V International The Year of RISC-V in a laptop TechTechPotato Andes Technology Interview at RISC-V Summit Europe 2023 RISC-V International

Discussions on the web

Recent threads on Reddit and Hacker News that mention RISC-V.

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Hacker News · u/mrLSD-dev · 

F# RISC-V v0.6.0 released

F# RISC-V v0.6.0 released

4

People also ask

Common questions on RISC-V, surfaced from across the indexed web.

How is video output generated and synchronized at 320x200 resolution from individual single-pixel MCUs?

Each MCU in bitluni’s build is assigned to generate one pixel of the 320x200 (QVGA) frame, so the full image is produced in parallel by 8,192 CH570 RISC-V microcontrollers. The cluster’s per-pixel outputs are combined to form the frame at QVGA resolution and driven as the video signal; timing and synchronization are achieved by coordinating the MCUs so they output their pixel values in the correct order for the 320x200 scanout. Answered

Engineer builds his own graphics card because modern GPUs are too expensive
What’s Up with RISE?

So what’s this impressive list of RISC-V movers and shakers actually doing with RISE?  The RISE Project focuses on commercial product readiness, key for the adoption of RISC-V technologies in market segments such as mobile, datacenter, consumer electronics, datacenter and automotive. RISE's mission is to accelerate the development of open source software for the RISC-V architecture. Members share a roadmap, technical contributions, staffing and funding for critical projects across a wide set of project categories, such as compilers and toolchains, debug and profiling, Linux distribution integr

Rising to the challenge of RISC-V software readiness
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