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Transistor

tomshardware.com › tech-industry › semiconductors

Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer

… Building the transistor upside down Contact resistance has been the dominant obstacle to scaling 2D transistors because an atomically thin channel carries comparatively little current, and the junction between the metal contact and the 2D film tends to throttle whatever the channel can deliver, par… …

Jun 19, 2026 · Luke James

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tomshardware.com › tech-industry › semiconductors

Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repair to ease AI's memory bottleneck

… Conventional DRAM cells are built in the front-end-of-line, the base silicon layer where transistors are normally fabricated. XBM instead moves the 1T1C cell into the back-end-of-line, the metal-and-via stack above the transistor layer, using thin-film transistors. …

Jul 7, 2026 · Etiido Uko
tomshardware.com › tech-industry › semiconductors

Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law

Huawei has announced a new chip design framework aimed at closing the technology gap with global semiconductor leaders like TSMC and Nvidia, targeting '1.4nm-class' transistors and a 55% increase in transistor density. …

May 25, 2026 · Etiido Uko
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