TSMC
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Intel "Razor Lake" to Use TSMC's N2X Node, Brings bLLC to Laptop SKUs
Intel's "Razor Lake" is a next-generation processor lineup set to launch after the upcoming "Nova Lake" Core Ultra 400 series, scheduled for early 2027. Today, we learn that Intel is planning some "Ra
NVIDIA's next-gen 'Feynman' GPUs to be built with TSMC's 1.6 nm A16 process
NVIDIA will skip TSMC's N2 or 2nm process for the 'Feynman' generation and go straight to the more advanced TSMC A16 1.6nm process.
A 0.42-Nanometer Breakthrough From TSMC Could Push Transistors Beyond Silicon - Semiwiki
Researchers at National Yang Ming Chiao Tung University and TSMC Corporate Research engineered a 0.42-nanometer aluminum-oxide interface that protects electron transport in monolayer MoS₂ transistors
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Inside TSMC Arizona: Building Sustainable Manufacturing in the Phoenix Community
Inside TSMC Arizona: Building America’s Advanced Semiconductor Future
From Groundbreaking to Game-changing: NVIDIA Blackwell Volume Production Celebration at TSMC Arizona
TSMC Arizona: A Journey of Innovation and Collaboration
TSMC Arizona Process Technician
TSMC Arizona Equipment Technician
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Which TSMC process node is NVIDIA reportedly using for Feynman, and how does it compare to Rubin/Rubin Ultra?
The report says NVIDIA is targeting TSMC's A16 1.6 nm process for Feynman. This is a jump from Rubin and Rubin Ultra, which are based on TSMC's N3 (3 nm) process. Answered
NVIDIA's next-gen 'Feynman' GPUs to be built with TSMC's 1.6 nm A16 processWhy is skipping TSMC's N2/2nm process notable for NVIDIA's Feynman GPUs?
Skipping TSMC's N2/2nm process is notable because NVIDIA is jumping straight to TSMC's more advanced A16 1.6nm node for Feynman, representing a major node shrink from the 3nm Rubin architectures. The move is also significant because Feynman will be NVIDIA's first technology to use 3D chiplets via TSMC's SoIC technology, backside power delivery, and next-generation packaging, along with custom next-generation HBM and co-packaged optics to boost performance and bandwidth. Answered
NVIDIA's next-gen 'Feynman' GPUs to be built with TSMC's 1.6 nm A16 processWhat is InFO-PoP packaging and why does it require DRAM before TSMC can ship the A20 chips to Apple?
InFO-PoP is Integrated Fan-Out Package on Package technology that stacks the DRAM memory directly above the main SoC, eliminating a separate LPDDR5X module and saving physical space. Because the memory must be physically integrated into the processor package at TSMC, TSMC cannot complete packaging or ship the A20 chips to Apple until the required DRAM is delivered and installed, a process that the article says takes about two weeks to finish. Answered
$1 billion in TSMC chips for Apple's new iPhone 18 are reportedly sitting on shelves, waiting for DRAMWhat does the article say about the $1 billion in TSMC inventory and why it’s considered ‘excess’?
The article says TSMC is reportedly holding on to over $1 billion of "excess inventory" because the wafers/chips cannot be fully packaged and shipped without the DRAM that must be integrated using InFO-PoP technology. InFO-PoP requires the DRAM to be stacked above the SoC before processors can leave TSMC, so the inventory is considered excess while it waits for the missing DRAM and Apple scrambles to secure it. Answered
$1 billion in TSMC chips for Apple's new iPhone 18 are reportedly sitting on shelves, waiting for DRAM