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Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core

ContextCNX SoftwareTechPowerUpView all sources →

Also known as risc-v international·risc-v cpu·risc-v processor·risc-v architecture·risc-v chip

1.1 Activity score up · 4d
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Key Takeaway Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core
AI summary · grounded in cited sources
SourcesCNX SoftwareTechPowerUpView all sources →
risc-v international risc-v cpu risc-v processor risc-v architecture risc-v chip
Positive 78/100
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Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core

Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core

Trending Activity ▼ -1.3 24h
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Top 4 signals · recent activity
CNX Software · 4h ago
Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core
r/hardware · 1d ago
NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC
CNX Software · 2d ago
OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations
Phoronix · 2d ago
Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

Recent signals

  • Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core CNX Software
  • NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC TechPowerUp
  • SpacemiT shows off usably quick RISC-V mini desktop Phoronix
  • Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds Phoronix
Source-backed brief 4 articles across 3 publications · brief is source backed Show all sources
CNX Software · 2 articles
Phoronix · 1 article
r/hardware · 1 article

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View all 10 signals →
techpowerup.com

NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC

NextSilicon, a leader in next-generation computing solutions for AI and high-performance computing (HPC), today announced plans to productize its Arbel RISC-V core into a 64-core and a 128-core, enter

2d ago
cnx-software.com

OpenCV 5 release - New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations - CNX Software

OpenCV 5 open-source computer vision library has recently been released with a brand-new DNN (Deep Neural Network) engine that provides better ONNX

2d ago Jean-Luc Aufranc (CNXSoft)
phoronix.com

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

An important one-liner is set to come for Linux 7.2 to enable ESWIN SoC support by default for RISC-V kernel builds

2d ago
phoronix.com

RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

Recently I published some initial SpacemiT K3 benchmarks for that first-to-market RISC-V RVA23 SoC with the K3 Pico-ITX mini computer.

3d ago
phoronix.com

Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline

The open-source developers at Georgia Tech working on Vortex as an OpenCL-compatible RISC-V GPGPU implementation are out with their next major release for this open-source GPU design.

3d ago
phoronix.com

Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support

Following the official Fedora 44 images released one month ago, Fedora 44 RISC-V images were published today for those wanting to run this newest Fedora Linux on RISC-V hardware.

3d ago

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CNX Software 2 articles

Tracking: Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core / OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations

Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations
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The Year of RISC-V in a laptop TechTechPotato Andes Technology Interview at RISC-V Summit Europe 2023 RISC-V International

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Hacker News · u/mrLSD-dev · 

F# RISC-V v0.6.0 released

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What’s Up with RISE?

So what’s this impressive list of RISC-V movers and shakers actually doing with RISE?  The RISE Project focuses on commercial product readiness, key for the adoption of RISC-V technologies in market segments such as mobile, datacenter, consumer electronics, datacenter and automotive. RISE's mission is to accelerate the development of open source software for the RISC-V architecture. Members share a roadmap, technical contributions, staffing and funding for critical projects across a wide set of project categories, such as compilers and toolchains, debug and profiling, Linux distribution integr

Rising to the challenge of RISC-V software readiness
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