Followed topics

RISC-V

More context

News around RISC-V is currently split between new hardware momentum (NextSilicon’s 64-core AI/HPC processor effort and SpacemiT’s RISC-V mini desktop) and rapid software ecosystem updates (Linux 7.2 enabling ESWIN SoC support by default). Parallel to that, graphics acceleration progress is highlighted by Vortex 3.0, a full-stack open-source RISC-V GPU release.

Context

Phoronix View all sources →

Also known as risc-v international·risc-v cpu·risc-v processor·risc-v architecture·risc-v chip

1.7 Activity score down · 4d

3.5 Peak score 4d window

Positive Sentiment

4 Sources · 7 signals

30m ago Last updated · next ~17:30

4d First on radar

Key Takeaway RISC-V momentum is accelerating on both the hardware side (64-core AI/HPC and usable desktops) and the software side (Linux 7.2 kernel build support plus a major open-source GPU update).

AI summary · grounded in cited sources

Sources

TechPowerUp View all sources →

AI/HPC enterprise chips RISC-V desktop hardware Linux kernel enablement Open-source GPU progress risc-v international

Positive 78/100

Themes

RISC-V desktop hardware Linux kernel enablement

+2 adjacent themes

AI/HPC enterprise chips Open-source GPU progress

AI Brief

RISC-V momentum is accelerating on both the hardware side (64-core AI/HPC and usable desktops) and the software side (Linux 7.2 kernel build support plus a major open-source GPU update).

News around RISC-V is currently split between new hardware momentum (NextSilicon’s 64-core AI/HPC processor effort and SpacemiT’s RISC-V mini desktop) and rapid software ecosystem updates (Linux 7.2 enabling ESWIN SoC support by default). Parallel to that, graphics acceleration progress is highlighted by Vortex 3.0, a full-stack open-source RISC-V GPU release.

Trending Activity ▼ -0.8 24h

Trend score · left axis Sentiment score · right axis

Live Wire

Top 2 signals · RISC-V momentum is accelerating

Phoronix · 22h ago

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

CNX Software · 2d ago

OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations

Broader RISC-V coverage

Other RISC-V activity — not part of the “RISC-V momentum is accelerating” story

r/hardware · 12h ago

NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC

Phoronix · 2d ago

RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

Briefing Findings · RISC-V momentum is accelerating

Story-specific findings extracted from this briefing's coverage. Fast Facts in the sidebar holds the canonical reference data (CEO, founded, ticker).

NextSilicon CPU cores 64-core RISC-V enterprise processor

Linux version Linux 7.2

Linux change ESWIN SoC support enabled by default for RISC-V kernel builds

What to Watch

Watch for follow-on coverage as Linux 7.2 RISC-V ESWIN SoC support rolls into mainstream kernel builds. Phoronix
Track updates on NextSilicon’s Arbel RISC-V core road map for the promised 64-core enterprise AI/HPC processor. TechPowerUp

What Changed

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds Phoronix
OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations CNX Software

Source-backed brief 3 articles across 3 publications · brief is source backed Show all sources

CNX Software · 1 article

OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations

Phoronix · 1 article

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

r/hardware · 1 article

NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC

Broader RISC-V coverage · not part of the RISC-V momentum is accelerating story

Phoronix · 1 article

RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

Latest from across the web

External coverage we have crawled and indexed for this topic.

View all 10 signals →

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

An important one-liner is set to come for Linux 7.2 to enable ESWIN SoC support by default for RISC-V kernel builds

cnx-software.com

OpenCV 5 release - New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations - CNX Software

OpenCV 5 open-source computer vision library has recently been released with a brand-new DNN (Deep Neural Network) engine that provides better ONNX

2d ago Jean-Luc Aufranc (CNXSoft)

Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support

Following the official Fedora 44 images released one month ago, Fedora 44 RISC-V images were published today for those wanting to run this newest Fedora Linux on RISC-V hardware.

techpowerup.com

NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC

NextSilicon, a leader in next-generation computing solutions for AI and high-performance computing (HPC), today announced plans to productize its Arbel RISC-V core into a 64-core and a 128-core, enter

Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline

The open-source developers at Georgia Tech working on Vortex as an OpenCL-compatible RISC-V GPGPU implementation are out with their next major release for this open-source GPU design.

RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

Recently I published some initial SpacemiT K3 benchmarks for that first-to-market RISC-V RVA23 SoC with the K3 Pico-ITX mini computer.

What each outlet is saying

Source-by-source view of what publications and communities are surfacing right now.

Phoronix 3 articles

Tracking: Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds / RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3

+1 more

Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline

r/hardware Community · 1 article

Tracking: NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC / SpacemiT shows off usably quick RISC-V mini desktop

NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC

TechPowerUp 1 article

Tracking: (PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC

(PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC

CNX Software 1 article

Tracking: OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations

OpenCV 5 release – New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations

Discovery

Videos

Topic-matched media from the channels we track

The Year of RISC-V in a laptop TechTechPotato 2d ago Andes Technology Interview at RISC-V Summit Europe 2023 RISC-V International 8d ago

Discussions on the web

Recent threads on Reddit and Hacker News that mention RISC-V.

More in search →

Hacker News · u/mrLSD-dev · 9d ago

F# RISC-V v0.6.0 released

F# RISC-V v0.6.0 released

People also ask

Common questions on RISC-V, surfaced from across the indexed web.

What’s Up with RISE?

So what’s this impressive list of RISC-V movers and shakers actually doing with RISE? The RISE Project focuses on commercial product readiness, key for the adoption of RISC-V technologies in market segments such as mobile, datacenter, consumer electronics, datacenter and automotive. RISE's mission is to accelerate the development of open source software for the RISC-V architecture. Members share a roadmap, technical contributions, staffing and funding for critical projects across a wide set of project categories, such as compilers and toolchains, debug and profiling, Linux distribution integr

Rising to the challenge of RISC-V software readiness

Share & embed Quotables, social share, embed snippet

Share

Quotables · click to copy

Verbatim claims you can cite from the briefing. Each quote is sourced from indexed coverage — paste into your own writing or social.

Embed widget

<script src="https://ttek2.com/embed/pulse/risc-v" async></script>