QSOE v0.1 Released As A QNX-Inspired RISC-V OS
QSOE v0.1 Released As A QNX-Inspired RISC-V OS Written by Michael Larabel in Operating Systems on 24 June 2026 at 06:05 AM EDT. 2 Comments QSOE 0.1…
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RISC-V
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RISC-V is being advanced simultaneously in operating-system support and in new high-integration, performance-focused hardware cores/MCUs.
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Top stories
StarFive Dubhe-100 - A 64-bit, RVA23-compliant RISC-V core for high-performance applications - CNX Software
1d agoAlibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds
2d agoWCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM - CNX Software
1w agoComu is a $6 tiny CH32V203 RISC-V development board that fits inside a USB port - CNX Software
1w agoRufus improves Windows installs, adds RISC-V and UEFI:NTFS fixes
…Version 4.15 brings RISC-V 64 support to UEFI:NTFS, improves unattended Windows installations, and fixes Snapdragon X Arm64 boot crashes, and more.Read Entire Article
PoCL 7.2-RC1 Brings Official OpenCL 3.0 Conformance On RISC-V & x86_64 CPUs
PoCL 7.2-RC1 Brings Official OpenCL 3.0 Conformance On RISC-V & x86_64 CPUs Written by Michael Larabel in Programming on 7 August 2026 at 09:39 AM EDT. Add…
NetBSD 11.0 Released With RISC-V Support, Enhanced Linux System Call Compatibility
NetBSD 11.0 Released With RISC-V Support, Enhanced Linux System Call Compatibility Written by Michael Larabel in BSD on 1 August 2026 at 12:49 PM EDT. 4 Comments NetBSD 11…
Discussions and forums
F# RISC-V v0.6.0 released
F# RISC-V v0.6.0 released
4
Creating your own RISC-V processor, SoC and board with Claude
Creating your own RISC-V processor, SoC and board with Claude
6
1
Milk-V Jupiter 2: RISC-V RVA23 SBC
submitted by /u/3G6A5W338E to r/hardware [link] [comments]
Alibaba's RISC-V CPU, XuanTie C950, Runs Qwen-3.8 27B at 30 tps
Who needs GPUs? submitted by /u/DeltaSqueezer to r/LocalLLaMA [link] [comments]
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor
4
Xen 4.22 Released With AMD Zen 5 BLT Support, Improved RISC-V Virtualization
Xen 4.22 Released With AMD Zen 5 BLT Support, Improved RISC-V Virtualization Written by Michael Larabel in Virtualization on 30 July 2026 at 09:45 AM EDT. Add A Comment…
Rising to the challenge of RISC-V software readiness
…In this manner, the RISE Project and RISC-V International are fully complementary to each other. Intel is excited to be a part of this new important leg of the RISC-V…
RVCC Proposed As An LLVM Incubator For High Performance RISC-V Optimizations
RVCC Proposed As An LLVM Incubator For High Performance RISC-V Optimizations Written by Michael Larabel in LLVM on 30 March 2026 at 09:42 AM EDT. 12 Comments A proposal was…
S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development - Semiwiki
S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development by Daniel Nenni on 12-16-2025 at 10:00 am View Forum Posts View Articles Private Message…
AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk - Semiwiki
…Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk by Daniel Nenni on 06-22-2026 at 10:00 am View Forum Posts View Articles Private Message Categories: Aion Silicon…
Samsung Takes First Step Away From ARM's Ecosystem By Working On An SSD Controller Chip Based On RISC-V Architecture
…Even so, Samsung is apparently taking its first tentative steps towards the open-source RISC-V architecture via a custom SSD controller chip. Samsung is tentatively exploring the RISC-V open-source…