Intel Razor Lake-AX detailed in new rumor - KitGuru
Intel Razor Lake-AX detailed in new rumor João Silva 11 hours ago Graphics New rumors suggest that Intel's upcoming “Razor Lake-AX” processors will utilise on-package memory and high…
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NVIDIA's Next-Gen Rosa CPU To Feature Rigel "Arm v9.2" Cores With Larger L2 Cache & Higher Per-Core Performance In The Same Silicon Footprint
1d agoIntel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer — backend-transistor DRAM stack uses UCIe links and built-in repair to ease AI's memory bottleneck
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1w agoJEDEC releases new SPHBM4 standard to slash AI memory costs — Narrow 512-bit interface enables dropping expensive interposers for organic substrates
…HBM4 performance with a 512-bit wide interface Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside…
IMEC Thinks CFET Stacks Will Let Chips Keep Scaling Into the 2030s
…new ways to better electrically separate the top and bottom transistor from each other, so they can work independently. The process that would make that possible is complicated. The silicon and silicon…
Anthropic in early talks to buy DRAM-less AI inference chips from UK startup — Fractile's SRAM architecture reduces need for pricey memory during extreme pricing and shortage crunch
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Discussions and forums
Show HN: TurboQuant for mlx-lm (Apple Silicon)
Hi HN,I built mlx-turboquant, an implementation of Google's TurboQuant KV-cache compression algorithm for Apple's MLX framework.The repository includes quality benchmarks, memory benchmarks, and a modular implementation …
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Ask HN: What are some good/fast coding models for Apple Silicon?
I have an M4 Max with 128 GB of unified memory, and I thought it would be easy to reach decent inference speeds with it. After a few failed attempts to exceed about 150 t/s with completely custom Metal inference engines …
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Exclusive: China targets 70% advanced domestic silicon wafer use by 2026
According to Nikkei Asia, China is working on more than 70% of the silicon wafers used by domestic chipmakers by the end of this year. This goal demonstrates China’s most aggressive attempt to localize key semiconductor …
Show HN: Covalence – Cross-Client Memory for Claude, Cursor, and MCP (macOS)
I use Claude Desktop, Claude Code, and Cursor daily. They all have memory now, but none of them share it. Something I explained in Claude Desktop doesn't exist when I open Cursor. I got tired of re-explaining my stack, m…
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Show HN: OS Megakernel that match M5 Max Tok/w at 2x the Throughput on RTX 3090
Hey there, we fused all 24 layers of Qwen3.5-0.8B (a hybrid DeltaNet + Attention model) into a single CUDA kernel launch and made it open-source for everyone to try it.On an RTX 3090 power-limited to 220W: - 411 tok/s vs…
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Efficient General Intelligence - When Novel Models Meet Customized Silicons
Efficient General Intelligence - When Novel Models Meet Customized Silicons Learn about the opportunities and progress for AI models and hardware accelerator co-design for efficient general intelligence (EGI), e.g. hierarchical memory…
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Advancing AI Infrastructure for Agentic AI with NVIDIA DOCA In-Silicon Security | NVIDIA Technical Blog
…BlueField-4 silicon, a new class of NVIDIA DOCA security capabilities extends protection across the full AI lifecycle and the Vera Rubin platform. Whether safeguarding AI models, context memory, datasets, or runtime…
Lexar Introduces Dedicated AI Solutions While Pushing Its Pro & Play SSDs To New Heights, ROG Certified ARES DDR5 Also Unveiled
…Lexar also showcased its ARES RGB DDR5 memory, which is ROG Certified and delivers fast performance when paired with ASUS's ROG motherboards. The memory supports Ultra Low Latency CL28 timings and…
Build Your Own Steam Machine with Four Configurations, from Budget to Premium
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SK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers
SK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI…