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RISC-V Summit 2019: 23 Avoiding Amdahl's Law RISC-V Architecture Exploration for AI & ML Compute
The Year of RISC-V in a laptop
AMD, Intel, Arm, RISC-V, IBM / The AI Hardware Show S2E3
Intel, AMD, Arm, RISC-V / The AI Hardware Podcast S2E3
Andes Technology Interview at RISC-V Summit Europe 2023
Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann
Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions -Roger Espasa, Semidynamics
RISC V & SoC Architectural Exploration for AI and ML accelerators
Hackers "RISC Architecture is gonna Change Everything"
…Two key technologies, RISC-V* and SYCL*, are noteworthy examples of this design mode. They exemplify the modern movement toward developing applications that exploit the capabilities of multiarchitecture systems. RISC-V offers…
Accelerating AI with RISC-V ISA by Daniel Nenni on 06-10-2026 at 2:00 pm View Forum Posts View Articles Private Message Categories: Andes Technology , IP Key takeaways ▼ Lessons from…
SpacemiT K3 is an upcoming RVA23-compliant 64-bit RISC-V processor based on X100 cores clocked at up to 2.5 GHz. So far, we had limited information, but SpacemiT gave…
Wer gedacht hat, dass sich NVIDIA weiterhin brav ins Hochzeitsbett mit ARM kuschelt, während man heimlich AMD GPUs verdrängt, hat wohl das Geklapper in der RISC-V-Werkstatt überhört. Denn was hier…
F# RISC-V v0.6.0 released
Creating your own RISC-V processor, SoC and board with Claude
submitted by /u/3G6A5W338E to r/hardware [link] [comments]
Who needs GPUs? submitted by /u/DeltaSqueezer to r/LocalLLaMA [link] [comments]
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor
Western Digital has announced that it's completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code…
…The chip is a big step-up for the platform, with two RISC-V cores running at 400 MHz. It is supported by 32 MB of PSRAM and 16 MB of flash…
…Sipeed has launched its new K3 series Single Board Computers, powered by the RISC-V ISA. Using SpacemiT's new "Fusion Architecture" with dedicated matrix multiplication blocks, Sipeed claims these systems can…
DeepComputing today announced the official launch of the DC-ROMA RISC-V Mainboard III for the Framework Laptop 13, marking a major milestone in bringing practical, high-performance RISC-V computing into…
Similar to Linux 7.2 enabling Eswin SoC support by default in the RISC-V 'defconfig' kernel build, UltraRISC RISC-V coverage is also now being enabled by default for RISC-V…
Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds Written by Michael Larabel in RISC-V on 10 June 2026 at 02:42 PM EDT. Add…