Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds
Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds Written by Michael Larabel in RISC-V on 10 June 2026 at 02:42 PM EDT. Add…
Search
All sources
phoronix.com
26
cnx-software.com
20
semiwiki.com
19
wccftech.com
5
igorslab.de
5
tomshardware.com
5
intel.com
3
spectrum.ieee.org
3
heise.de
2
extremetech.com
2
techpowerup.com
1
tweaktown.com
1
Tracked topic
RISC-V
Live now
RISC-V is being advanced simultaneously in operating-system support and in new high-integration, performance-focused hardware cores/MCUs.
Videos
More videosTop stories
StarFive Dubhe-100 - A 64-bit, RVA23-compliant RISC-V core for high-performance applications - CNX Software
1d agoAlibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds
2d agoWCH CH32V407/467 RISC-V MCU integrates Fast Ethernet MAC + PHY, 480 Mbps USB 2.0 PHY, up to 8 MB on-chip PSRAM - CNX Software
1w agoPoCL 7.2-RC1 Brings Official OpenCL 3.0 Conformance On RISC-V & x86_64 CPUs
1w agoFür digitale Souveränität: RISC-V-Sicherheitschip aus Deutschland
Das „RISC‑V Secure Element“ der Fraunhofer-Institute IIS, AISEC und EMFT soll die digitale Souveränität europäischer Chips und Schaltungen stärken. Es lässt sich als Funktionsblock in andere Chips integrieren, aber auch…
BeagleV Ahead & Lichee Pi 4a RISC-V Boards To See Working WiFi With Linux 7.2
BeagleV Ahead & Lichee Pi 4a RISC-V Boards To See Working WiFi With Linux 7.2 Written by Michael Larabel in RISC-V on 8 June 2026 at 06:24 AM EDT…
NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
Wednesday, June 10th 2026 NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC Press Release by TheLostSwede Today, 15:30 Discuss (0 Comments) NextSilicon, a…
Discussions and forums
Linux 7.2-rc2 Raising The Default RISC-V 64-bit CPU Limit To 256 Cores
Linux 7.2-rc2 Raising The Default RISC-V 64-bit CPU Limit To 256 Cores Written by Michael Larabel in RISC-V on 4 July 2026 at 06:09 AM EDT…
Red Hat Releases Second Developer Preview Of RHEL 10 For RISC-V
Red Hat Releases Second Developer Preview Of RHEL 10 For RISC-V Written by Michael Larabel in Red Hat on 12 June 2026 at 11:56 AM EDT. Add A Comment Last…
HFI BIOS Aims To Provide A POST-Like Power On Screen & BIOS Setup Utility For RISC-V
HFI BIOS Aims To Provide A POST-Like Power On Screen & BIOS Setup Utility For RISC-V Written by Michael Larabel in Free Software on 12 July 2026 at 06:50 AM…
Akeana Collaborates with Samsung Electronics, Fast-Tracking RISC-V Customers and Ecosystem for Server and Agentic AI Silicon - Semiwiki
Akeana Collaborates with Samsung Electronics, Fast-Tracking RISC-V Customers and Ecosystem for Server and Agentic AI Silicon by Daniel Nenni on 06-15-2026 at 10:00 am View Forum Posts…
Modder builds 8,192-core GPU at home out of RISC-V microcontrollers — full "graphics card" draws over 2,000 watts of power, requires a 3D printer to program
…As for the chips themselves, they're QingKe CH570 RISC-V units , each with a 32-bit RISC-V CPU with a limited instruction set, running at up to 100 MHz. The…
Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline
Vortex 3.0 Released As Full-Stack, Open-Source RISC-V GPU Now With 3D Pipeline Written by Michael Larabel in Hardware on 9 June 2026 at 06:02 AM EDT. 3…