Tracked topic
When considering best-fit applications for RISC-V, the appeal of extending the instruction set and competitive pricing for storage and edge applications has been pretty clear. But I have always struggled…
At the recent RISC-V Now event hosted by Andes, the discussion underscored the fact that RISC-V is no longer just about instruction set architecture advantages or customizable cores. The real…
Last year, we noted three upcoming high-performance RISC-V SoCs to watch out for: Zhihe A210, SpacemiT K3 , and UltraRISC UR-DP1000. The K3 has already been launched, and I’ll…
…Espressif setzt hier auf zwei 32-Bit-RISC-V-Kerne mit bis zu 320 MHz Taktfrequenz. Einer der Kerne besitzt einen 128 Bit breiten Datenpfad, kann also größere Datenmengen auf einmal verarbeiten…
One of the pioneers of the original RISC instruction set has returned to the design table with a goal that's nothing short of massive. David Patterson wants to reinvent computing with…
…Two key technologies, RISC-V* and SYCL*, are noteworthy examples of this design mode. They exemplify the modern movement toward developing applications that exploit the capabilities of multiarchitecture systems. RISC-V offers…
Accelerating AI with RISC-V ISA by Daniel Nenni on 06-10-2026 at 2:00 pm View Forum Posts View Articles Private Message Categories: Andes Technology , IP Key takeaways ▼ Lessons from…
Wer gedacht hat, dass sich NVIDIA weiterhin brav ins Hochzeitsbett mit ARM kuschelt, während man heimlich AMD GPUs verdrängt, hat wohl das Geklapper in der RISC-V-Werkstatt überhört. Denn was hier…
Last month, I received the SpacemiT K3 Pico-ITX Chassis Kit based on the company’s K3 16-core RISC-V SoC, and started the review with an unboxing, a teardown, and…
Similar to Linux 7.2 enabling Eswin SoC support by default in the RISC-V 'defconfig' kernel build, UltraRISC RISC-V coverage is also now being enabled by default for RISC-V…
