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Intel, AMD, Arm, RISC-V / The AI Hardware Podcast S2E3
AMD, Intel, Arm, RISC-V, IBM / The AI Hardware Show S2E3
Andes Technology Interview at RISC-V Summit Europe 2023
Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions -Roger Espasa, Semidynamics
Hackers "RISC Architecture is gonna Change Everything"
Demo: From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem - Darren Jones
Charlie Su, President and CTO of Andes Technology, delivered a compelling keynote at the 2025 RISC-V Summit North America, asserting that RISC-V is primed to drive the burgeoning field of…
Start9’s “RISC-V Router” is powered by a SpacemiT K1 octa-core RISC-V processor paired with 4GB RAM and 16GB eMMC flash, and offers dual GbE networking, as well as…
WCH CH32V205 is a 32-bit RISC-V MCU clocked at up to 192 MHz with 32KB SRAM, 256KB flash, and a USB 2.0 high-speed Host/device interface with a…
NASA’s New RISC-V Space Chip Offers 100x Performance Boost for Future Mars Missions by Aaron Leong — Wednesday, May 13, 2026, 09:56 AM EDT NASA and Microchip Technology Inc. are…
F# RISC-V v0.6.0 released
I built a portable 1090 MHz ADS-B receiver and Meshtastic mesh radio on a LilyGo T-Display-P4 (~$100). An RTL-SDR dongle plugged into the USB Host port receives aircraft transponder signals, decoded in real-time on the E…
AMD MicroBlaze™ V Processor A flexible and efficient RISC-V soft processor IP Image Zoom Overview The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD adaptive…
Milk-V, a renowned hardware firm in the space of RISC-V products, has unveiled its newest "AI PC" focused mini-ITX motherboard, coming in support of AMD's flagship Radeon GPUs…
…The chip is a big step-up for the platform, with two RISC-V cores running at 400 MHz. It is supported by 32 MB of PSRAM and 16 MB of flash…
SpacemiT K3 is an upcoming RVA23-compliant 64-bit RISC-V processor based on X100 cores clocked at up to 2.5 GHz. So far, we had limited information, but SpacemiT gave…
Western Digital has announced that it's completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code…
…Sipeed has launched its new K3 series Single Board Computers, powered by the RISC-V ISA. Using SpacemiT's new "Fusion Architecture" with dedicated matrix multiplication blocks, Sipeed claims these systems can…
