Sipeed's new K3 RISC-V SBCs can run 30B-parameter LLMs at 10 tokens per second
… Sipeed has launched its new K3 series Single Board Computers, powered by the RISC-V ISA. …
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RISC-V
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RISC-V
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Expect RISC-V progress to come as much from ecosystem enablement (Linux/BSP) as from new SoCs that bundle real connectivity and memory.
Live sources:
CNX Software
People also ask
How is video output generated and synchronized at 320x200 resolution from individual single-pixel MCUs?
Each MCU in bitluni’s build is assigned to generate one pixel of the 320x200 (QVGA) frame, so the full image is produced in parallel by 8,192 CH570 RISC-V microcontrollers. The cluster’s per-pixel outputs are combined to form the frame at QVGA resolution and driven as the video signal; timing and synchronization are achieved by coordinating the MCUs so they output their pixel values in the correct order for the 320x200 scanout. Answered
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