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Showing top 58 results for "tooling integration"

tomshardware.com › tech-industry › semiconductors

TSMC says panel packaging won't replace CoWoS anytime soon for the largest future AI processors — wafer-level tech can scale to 58 massive dies in one package

… We can scale CoWoS all the way to 14X using wafer-level processes, and we also have wafer-level integration. … You can integrate 58 large reticle-sized dies together. So, there is still plenty of room for us to continue advancing wafer-level integration. …

Jun 16, 2026 · Anton Shilov
tomshardware.com › tech-industry › semiconductors

Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer

… University groups have pushed monolayer MoS 2 transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once. …

Jun 19, 2026 · Luke James