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… At the silicon level, the Arc G3 is a heavily modified version of "Panther Lake-U," with a Compute tile built on the Intel 18A foundry node. The Compute tile features a 2P+8E CPU complex, while the SoC tile has four additional low-power island E-cores. …
… The four Compute tiles talk to two I/O and Memory Hub IMH tiles built on an older foundry node such as Intel 3. Each of the two IMH tiles has an 8-channel DDR5 memory interface, for a total of 16 DDR5 memory channels on the package. …
… However, the latest supply chain information suggests that the company now intends to bring the majority of "Nova Lake" compute tile production in-house, with about 80-90% of the tiles being manufactured by Intel Foundry. …
… Given that it makes tile-based disaggregated client processors with SoC tiles made on TSMC nodes, it's possible that this chip could be a "Panther Lake" or "Nova Lake" derivative that combines Compute and a truncated SoC tile from Intel; with a GPU tile from NVIDIA. …
… However, the latest supply chain information suggests that the company now intends to bring the majority of "Nova Lake" compute tile production in-house, with about 80-90% of the tiles being manufactured by Intel Foundry. …
… The gpu tile is on intel 3, and with 64 EU's you would be pretty much the same size as the 12 core part 6 kondamin The gpu tile is on intel 3, and with 64 EU's you would be pretty much the same size as the 12 core part No I understand the GPU tile is on a different process, but since the only 18A p… …
… When it comes to the iGPU on Pantherlake, it is on a separate tile; Intel decided this time around it made sense to make a big iGPU tile with 12 XE units, fabbed at TSMC, can be cut down to 10 XE and a small iGPU tile 4 XE units, made on Intel's fabs . …
… Each Compute tile contains a CPU complex with 48 "Panther Cove" P-Cores and an L3 cache localized to the tile. …
… Above the CPU tiles, the slot width and fin width of the 40 fins measure 0.2 mm each. …
… Looking at Intel's current "Panther Lake" SoC, which integrates multiple smaller dies into a unified package, we observe that Intel has utilized its 18A node for the compute tile's production. This tile measures approximately 8.004 x 14.288 mm, resulting in a silicon area of 114.304 mm². …