… We have gone vertical with DRAM memory with HBM stacks, which is relatively simple given the low power draw of memory chips compared to the ASICs that shuttle data around and compute upon it. …
… What gives? “The key innovation in our dataflow architecture is that we can overlap computation and communication, meaning that the increase in compute and network bandwidth means that we don't need to have the latest are greatest specs in other areas,” Rodrigo Liang, co-founder and chief executive… …
… To get a feel for what is going on with memory up and down the hierarchy as it relates to HPC and AI systems, we sat down with Praveen Vaidyanathan, vice president and general manager of Data Center Business at Micron, to talk about all things memory and to get some sense as to the growing demand f… …
… That’s sets up Micron to be a $45 billion memory maker in fiscal 2026 – if not larger. hbm4e hbm4 hbm3e hbm flash dram datacenter store micron memory lpddr5
… So while HBM is in hot demand, it burns a lot of chips, and that is capacity in the memory fab that might be allocated to high performance DDR5 memory for servers but isn’t. …
… You can bet Sanjay Mehrotra, the company’s chief executive officer, is thinking a lot about that – and how to not overdo it and create a bust cycle. dram micron nand hbm4 store hbm3e hbm flash
… Here is what the R4 family of switches from Arista Networks looks like, and remember that all of the Jericho 3-class chips have SRAM buffers on chip and deep buffers in HBM stacked DRAM on the ASIC package: The family starts with the fixed-port 7020R leaf switches with 10 Gb/sec and 25 Gb/sec downl… …
… The choice of HBM3e means Google is doing a price/performance optimization on the memory. The HBM3e stacks are twelve DRAM chips high there is an error in the block diagram below , and the six stacks provide 216 GB of capacity and 6,528 GB/sec of bandwidth. …
… The issue is that designing AI hardware from top to bottom is an expensive proposition, and there is really only one foundry that can make and package the compute engine and networking chips, only three suppliers of HBM and high-end DRAM, and the capacity for main memory and flash memory and advanc… …
… While the transistors went up by 1.5X, the HBM memory capacity went up by 3.4X to 216 GB six stacks of twelve-high 3 GB chips for 36 GB per stack and memory bandwidth went up by 3.9X to 7 TB/sec thanks to having two more stacks and to moving to HBM 3E memory. …