… To pull this off, network-level orchestration must ensure minimal variability in the hops between chips. This cross-chip exchange is unavoidable in any SRAM-based architecture that can’t hold the model on a single chip. …
… Inference at this scale depends on extreme co-design across chips, system architecture, and software. …
… View all posts by Kristen Perez View all posts by Kristen Perez About Pawini Mahajan Pawini Mahajan is a senior product marketing manager for Semiconductor and EDA at NVIDIA, where she drives go-to-market strategy at the intersection of AI, accelerated computing, and chip design. …
… Direct chip-to-chip spine Designed for extreme low-latency inference, the LPX rack connects 256 LPUs as one. …
… In this design, performance is governed less by peak arithmetic throughput and more by how consistently the system can keep compute fed, which is why the LPX pairs 150 TB/s of on-chip memory bandwidth with high bandwidth scale-up chip-to-chip C2C communication per LPU. …
… Each tray includes four NVLink 6 switch chips, 28.8 TB/s of total tray bandwidth, and 14.4 TFLOPS of FP8 in-network compute. …
… From chips to systems: NVIDIA Vera Rubin superchip to DGX SuperPOD AI factory performance is not determined by individual chips in isolation, but by how those chips are composed into systems that can be deployed, operated, and scaled reliably. …
… Building the telco AI cloud stack AI can be understood as a 5-layer cake —energy, chips, infrastructure, models, and applications. …
… Guideline 4 : Let KH determine the parallelism strategy. …
… She has previously worked for Meta and Adobe, focusing on product strategy, product development, and go-to-market strategy. …