Tracked topic
…The fifth version of the popular CV library also adds support for Intel, Arm, Qualcomm, and RISC-V hardware acceleration, improved 3D vision, and various new core features such as new data…
…SoC – SpacemiT K3 CPU 8x 64-bit RISC-V X100 “big” cores clocked up to 2.4 GHz, RVA23 compliance; 130 KDMIPS performance ( similar to RK3588 ) 8x RISC-V A100 AI Cores…
…System-on-Module – K3-CoM260 SoC – SpacemiT K3 CPU 8x 64-bit RISC-V X100 “big” cores clocked up to 2.4 GHz, RVA23 compliance; 130 KDMIPS performance ( similar to RK3588 ) 8x…
…14:00 – 14:35 – Upstream Embedded Linux on RISC-V SBCs: The Past, Present, and Future by Marcel Ziswiler Last year, I gave a talk about running upstream embedded Linux on RISC…
…handle gpio-hogs only once – Fixes a behaviour change that breaks boot on Raspberry Pi 5 when using the firmware-supplied device tree RISC-V updates in Linux 7.1 RISC-V…
…RISC-V updates in Linux 7.0 There were a good number of changes and updates related to the RISC-V architecture, too: Add support for control flow integrity for userspace processes…
…ESP32P4C61-TINY Specifications Wireless Module – Wireless-Tag WT01P461-S1 (25 x 25mm) Microcontroller – ESP32-P4 MCU Dual-core RISC-V microcontroller @ 360/400 MHz with AI instructions extension and single-precision FPU…
…Microcontroller – Raspberry Pi RP2350A CPU Dual-core Arm Cortex-M33 processor @ 150 MHz Dual-core 32-bit RISC-V Hazard3 @ 150 MHz Up to two cores can be used at a time…
…SoC – Espressif Systems ESP32-C6FH8 CPU Single-core 32-bit RISC-V clocked up to 160 MHz Low-power RISC-V core @ up to 20 MHz Memory – 512KB SRAM Storage – 320KB ROM…
…SoC – Raspberry Pi RP2354B CPU Dual-core Arm Cortex-M33 @ 150 MHz with Arm Trustzone, Secure boot Dual-core 32-bit RISC-V Hazard3 @ 150 MHz (3-stage in-order pipeline; RV32IMAC…